Abstract
The aim of this project is to completely rewrite two legacy etherboot drivers present in iPXE: for VIA Rhine (VT6105M) and VIA Velocity (VT6122/VT6130) chipsets.
Deliverables
Deliverable | Week | Current status |
Investigate iPXE drivers API and PCI API | 1 | done |
Write skeleton for new VIA Rhine driver: probe and attach card, read EEPROM, communicate with MII PHY | 2, 3 | done |
Write send and receive (polling) support for VIA Rhine | 4, 5 | done |
Do functional and performance tests on driver | 6 | done |
Write skeleton for VIA Velocity driver: probe, attach, read EEPROM and PHY | 7, 8 | done |
Write send and receive support for VIA Velocity | 9, 10 | in progress |
Do functional and performance tests on driver | 11 | in progress |
Review the code and do final cleanup | 12 | not done |
Commit code and write documentation | 13 | not done |
Daily progress
2012.05.20: Write skeleton for VIA Rhine driver based on skeleton.[ch]. Chip reset, MII read/write and reading MAC address from chip is working.
2012.05.22: Code style cleanup, introduce rhine_reload_eeprom() function to reload EEPROM contents. Working on link status notifications.
2012.05.24: First packets are successfully sent using new Rhine driver!
2012.05.30: RX and TX now working - first successfull boot using new Rhine driver
2012.06.10: Code cleanup, working on link status changes notifications
2012.06.20: Rhine driver almost finished. Begun working on Velocity driver
2012.06.29: Skeleton for VIA Velocity driver done
2012.07.07: VIA Velocity initialization, reset, EEPROM read, MII access and link status reporting works.
2012.07.10: Working on to get first packet transmitted and received on VIA Velocity
2012.07.25: TX and RX working with some minor issues
2012.08.13: Interrupt support (for UNDI) is working for both chips.
Screenshots
Test plan
Functional tests: transferring images, link state and speed changes
Performance tests: transfer speed
Useful links